


set_property DRIVE 12 [get_ports {O_DP0_dp159_OE[0]}]
set_property PACKAGE_PIN C26 [get_ports DP_tx_hpd]






create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list design_1_wrapper_inst/design_1_i/VID_CLK_RST_hier/clk_wiz_0/inst/CLK_CORE_DRP_I/clk_inst/clk_out1]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 48 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {tpg/O_data3[0]} {tpg/O_data3[1]} {tpg/O_data3[2]} {tpg/O_data3[3]} {tpg/O_data3[4]} {tpg/O_data3[5]} {tpg/O_data3[6]} {tpg/O_data3[7]} {tpg/O_data3[8]} {tpg/O_data3[9]} {tpg/O_data3[10]} {tpg/O_data3[11]} {tpg/O_data3[12]} {tpg/O_data3[13]} {tpg/O_data3[14]} {tpg/O_data3[15]} {tpg/O_data3[16]} {tpg/O_data3[17]} {tpg/O_data3[18]} {tpg/O_data3[19]} {tpg/O_data3[20]} {tpg/O_data3[21]} {tpg/O_data3[22]} {tpg/O_data3[23]} {tpg/O_data3[24]} {tpg/O_data3[25]} {tpg/O_data3[26]} {tpg/O_data3[27]} {tpg/O_data3[28]} {tpg/O_data3[29]} {tpg/O_data3[30]} {tpg/O_data3[31]} {tpg/O_data3[32]} {tpg/O_data3[33]} {tpg/O_data3[34]} {tpg/O_data3[35]} {tpg/O_data3[36]} {tpg/O_data3[37]} {tpg/O_data3[38]} {tpg/O_data3[39]} {tpg/O_data3[40]} {tpg/O_data3[41]} {tpg/O_data3[42]} {tpg/O_data3[43]} {tpg/O_data3[44]} {tpg/O_data3[45]} {tpg/O_data3[46]} {tpg/O_data3[47]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 48 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {tpg/O_data1[0]} {tpg/O_data1[1]} {tpg/O_data1[2]} {tpg/O_data1[3]} {tpg/O_data1[4]} {tpg/O_data1[5]} {tpg/O_data1[6]} {tpg/O_data1[7]} {tpg/O_data1[8]} {tpg/O_data1[9]} {tpg/O_data1[10]} {tpg/O_data1[11]} {tpg/O_data1[12]} {tpg/O_data1[13]} {tpg/O_data1[14]} {tpg/O_data1[15]} {tpg/O_data1[16]} {tpg/O_data1[17]} {tpg/O_data1[18]} {tpg/O_data1[19]} {tpg/O_data1[20]} {tpg/O_data1[21]} {tpg/O_data1[22]} {tpg/O_data1[23]} {tpg/O_data1[24]} {tpg/O_data1[25]} {tpg/O_data1[26]} {tpg/O_data1[27]} {tpg/O_data1[28]} {tpg/O_data1[29]} {tpg/O_data1[30]} {tpg/O_data1[31]} {tpg/O_data1[32]} {tpg/O_data1[33]} {tpg/O_data1[34]} {tpg/O_data1[35]} {tpg/O_data1[36]} {tpg/O_data1[37]} {tpg/O_data1[38]} {tpg/O_data1[39]} {tpg/O_data1[40]} {tpg/O_data1[41]} {tpg/O_data1[42]} {tpg/O_data1[43]} {tpg/O_data1[44]} {tpg/O_data1[45]} {tpg/O_data1[46]} {tpg/O_data1[47]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 48 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {tpg/O_data2[0]} {tpg/O_data2[1]} {tpg/O_data2[2]} {tpg/O_data2[3]} {tpg/O_data2[4]} {tpg/O_data2[5]} {tpg/O_data2[6]} {tpg/O_data2[7]} {tpg/O_data2[8]} {tpg/O_data2[9]} {tpg/O_data2[10]} {tpg/O_data2[11]} {tpg/O_data2[12]} {tpg/O_data2[13]} {tpg/O_data2[14]} {tpg/O_data2[15]} {tpg/O_data2[16]} {tpg/O_data2[17]} {tpg/O_data2[18]} {tpg/O_data2[19]} {tpg/O_data2[20]} {tpg/O_data2[21]} {tpg/O_data2[22]} {tpg/O_data2[23]} {tpg/O_data2[24]} {tpg/O_data2[25]} {tpg/O_data2[26]} {tpg/O_data2[27]} {tpg/O_data2[28]} {tpg/O_data2[29]} {tpg/O_data2[30]} {tpg/O_data2[31]} {tpg/O_data2[32]} {tpg/O_data2[33]} {tpg/O_data2[34]} {tpg/O_data2[35]} {tpg/O_data2[36]} {tpg/O_data2[37]} {tpg/O_data2[38]} {tpg/O_data2[39]} {tpg/O_data2[40]} {tpg/O_data2[41]} {tpg/O_data2[42]} {tpg/O_data2[43]} {tpg/O_data2[44]} {tpg/O_data2[45]} {tpg/O_data2[46]} {tpg/O_data2[47]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 48 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {tpg/O_data0[0]} {tpg/O_data0[1]} {tpg/O_data0[2]} {tpg/O_data0[3]} {tpg/O_data0[4]} {tpg/O_data0[5]} {tpg/O_data0[6]} {tpg/O_data0[7]} {tpg/O_data0[8]} {tpg/O_data0[9]} {tpg/O_data0[10]} {tpg/O_data0[11]} {tpg/O_data0[12]} {tpg/O_data0[13]} {tpg/O_data0[14]} {tpg/O_data0[15]} {tpg/O_data0[16]} {tpg/O_data0[17]} {tpg/O_data0[18]} {tpg/O_data0[19]} {tpg/O_data0[20]} {tpg/O_data0[21]} {tpg/O_data0[22]} {tpg/O_data0[23]} {tpg/O_data0[24]} {tpg/O_data0[25]} {tpg/O_data0[26]} {tpg/O_data0[27]} {tpg/O_data0[28]} {tpg/O_data0[29]} {tpg/O_data0[30]} {tpg/O_data0[31]} {tpg/O_data0[32]} {tpg/O_data0[33]} {tpg/O_data0[34]} {tpg/O_data0[35]} {tpg/O_data0[36]} {tpg/O_data0[37]} {tpg/O_data0[38]} {tpg/O_data0[39]} {tpg/O_data0[40]} {tpg/O_data0[41]} {tpg/O_data0[42]} {tpg/O_data0[43]} {tpg/O_data0[44]} {tpg/O_data0[45]} {tpg/O_data0[46]} {tpg/O_data0[47]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 32 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {tpg/frame_rate[0]} {tpg/frame_rate[1]} {tpg/frame_rate[2]} {tpg/frame_rate[3]} {tpg/frame_rate[4]} {tpg/frame_rate[5]} {tpg/frame_rate[6]} {tpg/frame_rate[7]} {tpg/frame_rate[8]} {tpg/frame_rate[9]} {tpg/frame_rate[10]} {tpg/frame_rate[11]} {tpg/frame_rate[12]} {tpg/frame_rate[13]} {tpg/frame_rate[14]} {tpg/frame_rate[15]} {tpg/frame_rate[16]} {tpg/frame_rate[17]} {tpg/frame_rate[18]} {tpg/frame_rate[19]} {tpg/frame_rate[20]} {tpg/frame_rate[21]} {tpg/frame_rate[22]} {tpg/frame_rate[23]} {tpg/frame_rate[24]} {tpg/frame_rate[25]} {tpg/frame_rate[26]} {tpg/frame_rate[27]} {tpg/frame_rate[28]} {tpg/frame_rate[29]} {tpg/frame_rate[30]} {tpg/frame_rate[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 12 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {tpg/h_counter[0]} {tpg/h_counter[1]} {tpg/h_counter[2]} {tpg/h_counter[3]} {tpg/h_counter[4]} {tpg/h_counter[5]} {tpg/h_counter[6]} {tpg/h_counter[7]} {tpg/h_counter[8]} {tpg/h_counter[9]} {tpg/h_counter[10]} {tpg/h_counter[11]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 32 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list {tpg/res_h_active[0]} {tpg/res_h_active[1]} {tpg/res_h_active[2]} {tpg/res_h_active[3]} {tpg/res_h_active[4]} {tpg/res_h_active[5]} {tpg/res_h_active[6]} {tpg/res_h_active[7]} {tpg/res_h_active[8]} {tpg/res_h_active[9]} {tpg/res_h_active[10]} {tpg/res_h_active[11]} {tpg/res_h_active[12]} {tpg/res_h_active[13]} {tpg/res_h_active[14]} {tpg/res_h_active[15]} {tpg/res_h_active[16]} {tpg/res_h_active[17]} {tpg/res_h_active[18]} {tpg/res_h_active[19]} {tpg/res_h_active[20]} {tpg/res_h_active[21]} {tpg/res_h_active[22]} {tpg/res_h_active[23]} {tpg/res_h_active[24]} {tpg/res_h_active[25]} {tpg/res_h_active[26]} {tpg/res_h_active[27]} {tpg/res_h_active[28]} {tpg/res_h_active[29]} {tpg/res_h_active[30]} {tpg/res_h_active[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 32 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list {tpg/res_v_active[0]} {tpg/res_v_active[1]} {tpg/res_v_active[2]} {tpg/res_v_active[3]} {tpg/res_v_active[4]} {tpg/res_v_active[5]} {tpg/res_v_active[6]} {tpg/res_v_active[7]} {tpg/res_v_active[8]} {tpg/res_v_active[9]} {tpg/res_v_active[10]} {tpg/res_v_active[11]} {tpg/res_v_active[12]} {tpg/res_v_active[13]} {tpg/res_v_active[14]} {tpg/res_v_active[15]} {tpg/res_v_active[16]} {tpg/res_v_active[17]} {tpg/res_v_active[18]} {tpg/res_v_active[19]} {tpg/res_v_active[20]} {tpg/res_v_active[21]} {tpg/res_v_active[22]} {tpg/res_v_active[23]} {tpg/res_v_active[24]} {tpg/res_v_active[25]} {tpg/res_v_active[26]} {tpg/res_v_active[27]} {tpg/res_v_active[28]} {tpg/res_v_active[29]} {tpg/res_v_active[30]} {tpg/res_v_active[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
set_property port_width 32 [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list {tpg/res_v_total[0]} {tpg/res_v_total[1]} {tpg/res_v_total[2]} {tpg/res_v_total[3]} {tpg/res_v_total[4]} {tpg/res_v_total[5]} {tpg/res_v_total[6]} {tpg/res_v_total[7]} {tpg/res_v_total[8]} {tpg/res_v_total[9]} {tpg/res_v_total[10]} {tpg/res_v_total[11]} {tpg/res_v_total[12]} {tpg/res_v_total[13]} {tpg/res_v_total[14]} {tpg/res_v_total[15]} {tpg/res_v_total[16]} {tpg/res_v_total[17]} {tpg/res_v_total[18]} {tpg/res_v_total[19]} {tpg/res_v_total[20]} {tpg/res_v_total[21]} {tpg/res_v_total[22]} {tpg/res_v_total[23]} {tpg/res_v_total[24]} {tpg/res_v_total[25]} {tpg/res_v_total[26]} {tpg/res_v_total[27]} {tpg/res_v_total[28]} {tpg/res_v_total[29]} {tpg/res_v_total[30]} {tpg/res_v_total[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
set_property port_width 12 [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list {tpg/v_counter[0]} {tpg/v_counter[1]} {tpg/v_counter[2]} {tpg/v_counter[3]} {tpg/v_counter[4]} {tpg/v_counter[5]} {tpg/v_counter[6]} {tpg/v_counter[7]} {tpg/v_counter[8]} {tpg/v_counter[9]} {tpg/v_counter[10]} {tpg/v_counter[11]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
set_property port_width 32 [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list {tpg/res_h_total[0]} {tpg/res_h_total[1]} {tpg/res_h_total[2]} {tpg/res_h_total[3]} {tpg/res_h_total[4]} {tpg/res_h_total[5]} {tpg/res_h_total[6]} {tpg/res_h_total[7]} {tpg/res_h_total[8]} {tpg/res_h_total[9]} {tpg/res_h_total[10]} {tpg/res_h_total[11]} {tpg/res_h_total[12]} {tpg/res_h_total[13]} {tpg/res_h_total[14]} {tpg/res_h_total[15]} {tpg/res_h_total[16]} {tpg/res_h_total[17]} {tpg/res_h_total[18]} {tpg/res_h_total[19]} {tpg/res_h_total[20]} {tpg/res_h_total[21]} {tpg/res_h_total[22]} {tpg/res_h_total[23]} {tpg/res_h_total[24]} {tpg/res_h_total[25]} {tpg/res_h_total[26]} {tpg/res_h_total[27]} {tpg/res_h_total[28]} {tpg/res_h_total[29]} {tpg/res_h_total[30]} {tpg/res_h_total[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list tpg/h_blank]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list tpg/O_hsync]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list tpg/O_oddeven]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list tpg/O_vde]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list tpg/O_vsync]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list tpg/v_blank]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list videoSignal_sel]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
connect_debug_port u_ila_0/probe18 [get_nets [list DP0_tx_vid_enable]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
connect_debug_port u_ila_0/probe19 [get_nets [list DP0_tx_vid_hsync]]
create_debug_core u_ila_1 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
set_property port_width 1 [get_debug_ports u_ila_1/clk]
connect_debug_port u_ila_1/clk [get_nets [list design_1_wrapper_inst/design_1_i/vid_phy_controller_0/inst/gt_usrclk_source/txoutclk]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
set_property port_width 12 [get_debug_ports u_ila_1/probe0]
connect_debug_port u_ila_1/probe0 [get_nets [list {design_1_wrapper_inst/tx_lane0_tuser[0]} {design_1_wrapper_inst/tx_lane0_tuser[1]} {design_1_wrapper_inst/tx_lane0_tuser[2]} {design_1_wrapper_inst/tx_lane0_tuser[3]} {design_1_wrapper_inst/tx_lane0_tuser[4]} {design_1_wrapper_inst/tx_lane0_tuser[5]} {design_1_wrapper_inst/tx_lane0_tuser[6]} {design_1_wrapper_inst/tx_lane0_tuser[7]} {design_1_wrapper_inst/tx_lane0_tuser[8]} {design_1_wrapper_inst/tx_lane0_tuser[9]} {design_1_wrapper_inst/tx_lane0_tuser[10]} {design_1_wrapper_inst/tx_lane0_tuser[11]}]]
create_debug_port u_ila_1 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1]
set_property port_width 32 [get_debug_ports u_ila_1/probe1]
connect_debug_port u_ila_1/probe1 [get_nets [list {design_1_wrapper_inst/tx_lane0_tdata[0]} {design_1_wrapper_inst/tx_lane0_tdata[1]} {design_1_wrapper_inst/tx_lane0_tdata[2]} {design_1_wrapper_inst/tx_lane0_tdata[3]} {design_1_wrapper_inst/tx_lane0_tdata[4]} {design_1_wrapper_inst/tx_lane0_tdata[5]} {design_1_wrapper_inst/tx_lane0_tdata[6]} {design_1_wrapper_inst/tx_lane0_tdata[7]} {design_1_wrapper_inst/tx_lane0_tdata[8]} {design_1_wrapper_inst/tx_lane0_tdata[9]} {design_1_wrapper_inst/tx_lane0_tdata[10]} {design_1_wrapper_inst/tx_lane0_tdata[11]} {design_1_wrapper_inst/tx_lane0_tdata[12]} {design_1_wrapper_inst/tx_lane0_tdata[13]} {design_1_wrapper_inst/tx_lane0_tdata[14]} {design_1_wrapper_inst/tx_lane0_tdata[15]} {design_1_wrapper_inst/tx_lane0_tdata[16]} {design_1_wrapper_inst/tx_lane0_tdata[17]} {design_1_wrapper_inst/tx_lane0_tdata[18]} {design_1_wrapper_inst/tx_lane0_tdata[19]} {design_1_wrapper_inst/tx_lane0_tdata[20]} {design_1_wrapper_inst/tx_lane0_tdata[21]} {design_1_wrapper_inst/tx_lane0_tdata[22]} {design_1_wrapper_inst/tx_lane0_tdata[23]} {design_1_wrapper_inst/tx_lane0_tdata[24]} {design_1_wrapper_inst/tx_lane0_tdata[25]} {design_1_wrapper_inst/tx_lane0_tdata[26]} {design_1_wrapper_inst/tx_lane0_tdata[27]} {design_1_wrapper_inst/tx_lane0_tdata[28]} {design_1_wrapper_inst/tx_lane0_tdata[29]} {design_1_wrapper_inst/tx_lane0_tdata[30]} {design_1_wrapper_inst/tx_lane0_tdata[31]}]]
create_debug_port u_ila_1 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2]
set_property port_width 1 [get_debug_ports u_ila_1/probe2]
connect_debug_port u_ila_1/probe2 [get_nets [list design_1_wrapper_inst/tx_lane0_tready]]
create_debug_port u_ila_1 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3]
set_property port_width 1 [get_debug_ports u_ila_1/probe3]
connect_debug_port u_ila_1/probe3 [get_nets [list design_1_wrapper_inst/tx_lane0_tvalid]]
create_debug_core u_ila_2 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_2]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_2]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_2]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2]
set_property port_width 1 [get_debug_ports u_ila_2/clk]
connect_debug_port u_ila_2/clk [get_nets [list design_1_wrapper_inst/design_1_i/processor_subsystem/clk_wiz_0/inst/clk_out2]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe0]
set_property port_width 1 [get_debug_ports u_ila_2/probe0]
connect_debug_port u_ila_2/probe0 [get_nets [list DP1_rx_vid_vsync]]
create_debug_port u_ila_2 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe1]
set_property port_width 1 [get_debug_ports u_ila_2/probe1]
connect_debug_port u_ila_2/probe1 [get_nets [list DP1_rx_vid_hsync]]
create_debug_port u_ila_2 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe2]
set_property port_width 1 [get_debug_ports u_ila_2/probe2]
connect_debug_port u_ila_2/probe2 [get_nets [list DP1_rx_vid_enable]]
create_debug_port u_ila_2 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe3]
set_property port_width 1 [get_debug_ports u_ila_2/probe3]
connect_debug_port u_ila_2/probe3 [get_nets [list DP0_rx_vid_vsync]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk_200]
